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Parity Bit-Based CAM Architecture Design by abhishek panda is a document available to read on EtoBox.
This document summarizes a research paper that proposes a new content addressable memory (CAM) architecture based on parity bits to reduce power consumption. CAMs allow fast parallel searching but use significant power. The proposed parity bit CAM (PB-CAM) architecture stores a parity bit for each data word instead of multiple parameter bits. This greatly reduces the number of comparisons needed and the size of the parameter memory. Simulations showed the PB-CAM design consumed less power and had faster sea
- Author
- abhishek panda
- Language
- EN