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CMOS Logic Gates Design with Verilog by Murali Lekkala is a document available to read on EtoBox.

What is CMOS Logic Gates Design with Verilog about?

The document discusses designing logic gates at the transistor level using switch level modeling in Verilog. It covers modeling MOS switches, designing a CMOS inverter, NAND, NOR gates and a 2:1 MUX in Verilog using switch level modeling and verifying the designs with simulation.

Author

Murali Lekkala

Language

EN