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15.2 A 350mV Single-Rail SRAM Using A Custom-Logic-Bitcell in 2nm-CMOS-Nanosheet Technology For Mobile and Edge-AI Applications by howard777 is a document available to read on EtoBox.
This document presents a 350mV single-rail SRAM architecture utilizing a custom logic-bitcell in 2nm-CMOS-nanosheet technology, optimized for mobile and edge-AI applications. The design achieves a high density of 21.04Mb/mm² and a low dynamic power operation, with a read-access time of 102ps, making it suitable for CPU, GPU, and NPU caches. The implementation demonstrates significant power reduction and area efficiency compared to conventional SRAM designs, enabling operation across a wide voltage range fro
- Author
- howard777
- Language
- EN