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The document details the evaluation of a baseline RISC-V system implemented in C++ using AMD Vitis HLS on a Zynq-7000 FPGA. Functional correctness was confirmed through successful C-level simulations, and performance metrics indicated an estimated latency of 340 ns and resource utilization of 1,709 LUTs and 467 Flip-Flops. Additionally, it discusses the setup process, issues encountered with WSL, and the use of AI for documentation and interpreting synthesis reports.
- Author
- Hemil Prajapati
- Language
- EN