About this document
Design Verification with Formality Techniques by مهند القاضي is a document available to read on EtoBox.
The document discusses key concepts in design verification, focusing on Logic Cones and Compare Points, and highlights the challenges of design transformations that can affect verification. It details how Formality handles these transformations, requiring user guidance, and provides examples from Synopsys synthesis flow, including Internal Scan, Boundary Scan, and Clock Gating. The document emphasizes the importance of managing changes in logic functions and register boundaries during these processes.
- Author
- مهند القاضي
- Language
- EN