About this scholarly article

Proceedings International Test Conference 2001 (Cat. No.01CH37260) - Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability by Kessler, M.; Kiefer, G.; Leenstra, J.; Schunemann, K.; Schwarz, T.; Wunderlich, H.-J. is a scholarly article available to read on EtoBox.

Author

Kessler, M.; Kiefer, G.; Leenstra, J.; Schunemann, K.; Schwarz, T.; Wunderlich, H.-J.

Publisher

IEEE

Published

2001