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About this Engineering article
Simulation, Analysis and Verification of Substrate Currents for Layout Optimization of Smart Power ICs by Buccella, Pietro; Stefanucci, Camillo; Sallese, Jean-Michel; Kayal, Maher is a Engineering article available to read on EtoBox.
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Buccella, Pietro; Stefanucci, Camillo; Sallese, Jean-Michel; Kayal, Maher
- Publisher
- IEEE; Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers (IEEE) (ISSN 0885-8993)
- Published
- 2015
- Language
- EN
- Field
- Engineering (Physical Sciences)
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