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About this Engineering article
Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications by Upasana; R. Narang; M. Saxena; M. Gupta is a Engineering article available to read on EtoBox.
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Upasana; R. Narang; M. Saxena; M. Gupta
- Publisher
- IEEE; Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers (IEEE) (ISSN 0018-9383)
- Published
- 2015
- Language
- EN
- Field
- Engineering (Physical Sciences)