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Scalable NoC for Dynamic FPGA Applications by srinivas.raghav04 is a document available to read on EtoBox.

What is Scalable NoC for Dynamic FPGA Applications about?

The document presents two architectures for a dynamically scalable network-on-chip (NoC) designed to optimize power consumption for run-time reconfigurable applications. The first architecture scales columns of the NoC, while the second scales both rows and columns based on demand for reconfigurable intellectual properties (IPs). Implemented on a Virtex 6 FPGA, the results indicate significant power savings compared to traditional static architectures, enhancing resource sharing among IPs at runtime.

Author

srinivas.raghav04

Language

EN