About this document
High-Speed VLSI Three-Operand Adder by loganathanas.ece is a document available to read on EtoBox.
The document presents a novel high-speed and area-efficient VLSI architecture for a three-operand binary adder, which enhances computational efficiency in modular arithmetic applications such as cryptography and pseudo-random bit generation. The proposed architecture utilizes a parallel prefix adder with four-stage structures, resulting in reduced critical path delay, area-delay product, and power consumption compared to traditional designs. Implementation results demonstrate significant performance improve
- Author
- loganathanas.ece
- Language
- EN