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Design of 6T-SRAM Cell Using Dual Threshold Voltage Transistor by Abhijeet Kumar is a document available to read on EtoBox.

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The document discusses the design of a 6T-SRAM cell using dual threshold voltage transistors to reduce power consumption and improve performance. It presents the issues with single threshold voltage SRAM cells and proposes a 6T-SRAM cell with low threshold transistors for driving and high threshold transistors for latching. Simulation results show reductions in power, delay and improvements in write operation for the dual threshold voltage cell design.

Author

Abhijeet Kumar

Language

EN