About this scholarly article

IEEE Asian Solid-State Circuits Conference 2011 - An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation by Niitsu, Kiichi; Sakurai, Masato; Harigai, Naohiro; Yamaguchi, Takahiro J.; Kobayashi, Haruo is a scholarly article available to read on EtoBox.

Author

Niitsu, Kiichi; Sakurai, Masato; Harigai, Naohiro; Yamaguchi, Takahiro J.; Kobayashi, Haruo

Publisher

IEEE

Published

2011

Language

EN