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STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction execution by Islam Atta; Pinar Tözün; Xin Tong; Anastasia Ailamaki; Andreas Moshovos is a Computer Science article available to read on EtoBox.

What is STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction execution about?

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove some instruction stalls in exchange for error-prone instrumentation to the code base, or a sharp increase in the L1-I cache unit area and power. Others reduce instruction miss latency by better utilizing a shared L2 cache. SLICC [2], a recently proposed thread migration technique that exploits transaction instruction locality, is promising for high core counts but performs sub-optimally or may hurt performance when running on few cores. This paper corroborates that OLTP transactions exhibit significant intra- and inter-thread overlap in their instruction footprint, and analyzes the instruction stall reduction benefits. This paper presents STREX, a hardware, programmer-transparent technique that exploits typical transaction behavior to improve instruction reuse in first level caches. STREX time-multiplexes the execution of similar transactions dynamically on a single core so that instructions fetched by one transaction are reused

Who reads STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction execution?

Author

Islam Atta; Pinar Tözün; Xin Tong; Anastasia Ailamaki; Andreas Moshovos

Publisher

ACM

Published

2013

Language

EN

Field

Computer Science (Physical Sciences)