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Microprocessor Pipeline Design and Data Hazards by Thanh Trúc is a document available to read on EtoBox.
What is Microprocessor Pipeline Design and Data Hazards about?
The document discusses pipeline design for a microprocessor. It provides details on perfect pipelining such as splitting the original 140ps cycle time into 14 even stages of 10ps each, reducing execution time from 1.4ms to 140us. It also notes that instruction latency and throughput may be affected since maintaining a CPI of 1 with 14 stages is optimistic and no-ops may need inserting. The document then analyzes data dependencies in a code sample. It identifies which can be resolved via forwarding and whi
- Author
- Thanh Trúc
- Language
- EN