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Process-related and stress-induced changes in threshold voltage are major variability concerns in ultra-scaled CMOS transistors. The device designers consider this variability as an irreducible part of the design problem and use different circuit level optimization schemes to handle these variations. In this paper, we demonstrate how an increase in the negative steepness of the universal mobility relationship improves both the process-related (e.g., oxide thickness fluctuation, gate work-function fluctuation), as well as stress-induced or reliability-related (e.g., Bias Temperature Instability or BTI) parametric variation in CMOS technology. Therefore, we calibrate the universal mobility parameters to reflect the measured variation of negative steepness in uniaxially strained CMOS transistor. This allows us to study the extent of (process-related and stress-induced parametric) variation resilience in uniaxial strain technology by increasing the negative steepness of the mobility characteristics. Thus, we show that variability analysis in strained CMOS technology must consider the presence of self-compensation between mobility variation and threshold voltage variation, which leads t

Author

Islam, Ahmad Ehteshamul; Augustine, Charles; Roy, Kaushik; Alam, Muhammad Ashraful

Published

2017

Language

EN