About this document
Clock Transition Issues in Timing Analysis by A Nikhil is a document available to read on EtoBox.
The document discusses clock configuration settings for timing analysis, including parameters like period, transition, uncertainty, and latency. It highlights the issue of timing violations in block-level analysis due to optimistic assumptions about clock input transitions, which can vary and lead to skew at the top level. The document emphasizes that such violations must be addressed at the sub-chip level rather than the top level.
- Author
- A Nikhil
- Language
- EN