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About this Engineering article
Compact Modeling of Charge, Capacitance, and Drain Current in III–V Channel Double Gate FETs by Yadav, Chandan; Agrawal, Mayank; Agarwal, Amit; Chauhan, Yogesh Singh is a Engineering article available to read on EtoBox.
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Yadav, Chandan; Agrawal, Mayank; Agarwal, Amit; Chauhan, Yogesh Singh
- Publisher
- IEEE; Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers (IEEE) (ISSN 1536-125X)
- Published
- 2017
- Field
- Engineering (Physical Sciences)
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