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Can I read Gated-diode FinFET DRAMs: Device and circuit design-considerations on EtoBox?
Gated-diode FinFET DRAMs: Device and circuit design-considerations by Ajay N. Bhoj; Niraj K. Jha is a Engineering article available to read on EtoBox.
What is Gated-diode FinFET DRAMs: Device and circuit design-considerations about?
Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22nm node is questionable, on account of high leakage power consumption, performance degradation, and instability due to process variations. Recently, two-three transistor one gated-diode (2T/3T1D) DRAMs were proposed as alternatives to address the SRAM variability problem, with an emphasis on high-activity embedded cache applications. They are highly competitive to SRAM in terms of performance, while having a smaller power and area footprint at lower technology nodes. The current evolutionary trend in transistor structures is moving toward an era of multigate devices, which makes it necessary to identify design issues and advantages of gated-diode DRAMs implemented in a multigate technology. In this work, we address gated-diode DRAM design in FinFET technology using mixed-mode 2D-device simulations. We revisit the model of internal voltage gain in bulk gated diodes and extend it to provide quantitative insight into designing Fin gated diodes, that is, gated diodes in FinFET technology. To this effect, we propose FinFET variants of the bulk gated-diode configuration and identify parameters that are critical to enhancin
Who reads Gated-diode FinFET DRAMs: Device and circuit design-considerations?
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Ajay N. Bhoj; Niraj K. Jha
- Publisher
- ACM
- Published
- 2010
- Language
- EN
- Field
- Engineering (Physical Sciences)