About this scholarly article

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) - 0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application by Takao, Y.; Nakai, S.; Tagawa, Y.; Otsuka, S.; Sambonsugi, Y.; Sugiyama, K.; Oota, H.; Iriyama, Y.; Nanjyo, R.; Nagai, H.; Naitoh, K.; Nakamura, R.; Sekino, S.; Yamanoue, A.; Horiguchi, N.; Yamamoto, T.; Kojima, M.; Satoh, S.; Sugii, T.; Kase, M.; Suzuki, K.; Nakaishi, M.; Miyajima, M.; Ohba, T.; Hanyu, I.; Sugatani, S. is a scholarly article available to read on EtoBox.

Author

Takao, Y.; Nakai, S.; Tagawa, Y.; Otsuka, S.; Sambonsugi, Y.; Sugiyama, K.; Oota, H.; Iriyama, Y.; Nanjyo, R.; Nagai, H.; Naitoh, K.; Nakamura, R.; Sekino, S.; Yamanoue, A.; Horiguchi, N.; Yamamoto, T.; Kojima, M.; Satoh, S.; Sugii, T.; Kase, M.; Suzuki, K.; Nakaishi, M.; Miyajima, M.; Ohba, T.; Hanyu, I.; Sugatani, S.

Publisher

IEEE

Published

2002