Can I read Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06 - A novel framework for multilevel full-chip gridless routing on EtoBox?

Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06 - A novel framework for multilevel full-chip gridless routing by Chen, Tai-Chen; Chang, Yao-Wen; Lin, Shyh-Chang is a scholarly article available to read on EtoBox.

What is Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06 - A novel framework for multilevel full-chip gridless routing about?

Due to its great flexibility, gridless routing is desirable for nanometer circuit designs that use variable wire widths and spacings. Nevertheless, it is much more difficult than grid-based routing because of its larger solution space. In this paper, we present a novel "V-shaped" multilevel framework (called VMF) for full-chip gridless routing. Unlike the traditional "Λ-shaped" multilevel framework (inaccurately called the "Vcycle" framework in the literature), our VMF works in the V-shaped manner: top-down uncoarsening followed by bottom-up coarsening. Based on the novel framework, we develop a multilevel full-chip gridless router (called VMGR) for large-scale circuit designs. The top-down uncoarsening stage of VMGR starts from the coarsest regions and then processes down to finest ones level by level; at each level, it performs global pattern routing and detailed routing for local nets and then estimate the routing resource for the next level. Then, the bottom-up coarsening stage performs global maze routing and detailed routing to reroute failed connections and refine the solution level by level from the finest level to the coarsest one. We employ a dynamic congestion map to gui

Author

Chen, Tai-Chen; Chang, Yao-Wen; Lin, Shyh-Chang

Publisher

ACM Press

Published

2006

Language

EN