About this document

Xilinx Spartan 3e Stack Implementation by ali is a document available to read on EtoBox.

This document describes implementing a stack on a Xilinx Spartan 3e FPGA. It will use a block RAM component generated with CoreGen to store stack data. A register will track the stack pointer and logic will control pushing/popping data and assert full/empty flags. The stack will be an ascending, full stack using a RAM component with 8-bit width and 16 byte depth. A VHDL design entity and testbench will be created to test pushing/popping data to/from the stack.

Author

ali

Language

EN