About this scholarly article

18th International Symposium on VLSI Design and Test - Power optimized PLL implementation in 180nm CMOS technology by Sreehari, Patri; Devulapalli, Pavankumarsharma; Kewale, Dhananjay; Asbe, Omkar; Prasad, K S R Krishna is a scholarly article available to read on EtoBox.

Author

Sreehari, Patri; Devulapalli, Pavankumarsharma; Kewale, Dhananjay; Asbe, Omkar; Prasad, K S R Krishna

Publisher

IEEE

Published

2014