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Frequency and Yield Optimization Using Power Gates in Power-constrained Designs by Nam Sung Kim; Jun Seomun; Abhishek Sinkar; Jungseob Lee; Tae Hee Han; Ken Choi; Youngsoo Shin is a scholarly article available to read on EtoBox.

What is Frequency and Yield Optimization Using Power Gates in Power-constrained Designs about?

Manufactured dies exhibit a large spread of maximum frequency and leakage power due to process variations, which have been increasing with technology scaling. Reducing the spread is very important for maximizing the frequency and the yield of powerconstrained designs, because otherwise many dies that do not satisfy frequency or power constraints would be discarded. In this paper, we propose two optimization methods to improve the maximum operating frequency and the yield using power gates that already exist in many power-constrained designs. In the first method, we consider the designs of multiple cores, where each of them can be independently power-gated. When each core shows different frequencies due to within-die variations, the strength of a power gate in each core is adjusted to make their maximum operating frequencies even. This allows faster cores to consume less active leakage power, reducing the total power consumption well below a power constraint in a globally-clocked design. We subsequently increase global supply voltage for higher overall frequency until the power constraint is satisfied. In our experiments assuming multicore processors with 2~16 cores, the maximum ope

Author

Nam Sung Kim; Jun Seomun; Abhishek Sinkar; Jungseob Lee; Tae Hee Han; Ken Choi; Youngsoo Shin

Publisher

ACM

Published

2009

Language

EN