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MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications by Rahman, Tousif; Mao, Gang; Maheshwari, Sidharth; Shafik, Rishad; Yakovlev, Alex is a scholarly article available to read on EtoBox.

What is MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications about?

System-on-Chip Field-Programmable Gate Arrays (SoC-FPGAs) offer significant throughput gains for machine learning (ML) edge inference applications via the design of co-processor accelerator systems. However, the design effort for training and translating ML models into SoC-FPGA solutions can be substantial and requires specialist knowledge aware trade-offs between model performance, power consumption, latency and resource utilization. Contrary to other ML algorithms, Tsetlin Machine (TM) performs classification by forming logic proposition between boolean actions from the Tsetlin Automata (the learning elements) and boolean input features. A trained TM model, usually, exhibits high sparsity and considerable overlapping of these logic propositions both within and among the classes. The model, thus, can be translated to RTL-level design using a miniscule number of AND and NOT gates. This paper presents MATADOR, an automated boolean-to-silicon tool with GUI interface capable of implementing optimized accelerator design of the TM model onto SoC-FPGA for inference at the edge. It offers automation of the full development pipeline: model training, system level design generation, design v

Author

Rahman, Tousif; Mao, Gang; Maheshwari, Sidharth; Shafik, Rishad; Yakovlev, Alex

Published

2024

Language

EN