About this document
High-Level Synthesis for FPGA Acceleration by yehia.mahmoud02 is a document available to read on EtoBox.
The document outlines a course on High-Level Synthesis (HLS) for multimedia System-on-Chip design, emphasizing application acceleration and the use of FPGAs with programming languages like C, C++, and Python. It details the course objectives, logistics, and contents, including lectures, labs, and project presentations aimed at empowering software designers. The course also highlights the importance of HLS in enhancing productivity, IP reuse, and application acceleration in computing architecture.
- Author
- yehia.mahmoud02
- Language
- EN