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This paper explores inverter designs using co-optimized n- and p-type tunnel field-effect transistors (TFETs) on an InAs/Al0.05Ga0.95Sb platform for low-voltage and low-power applications. The proposed TFET inverters demonstrate significantly improved performance compared to traditional CMOS logic, particularly in low operating power scenarios, with potential for faster operation and reduced power consumption. The study highlights the importance of device geometry and doping levels in achieving optimal perf

Author

arup

Language

EN