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This document summarizes a lab demonstration of the first order sinusoidal steady state response of an inverting amplifier and RC circuit. As the input frequency is increased from 2 kHz to 20 kHz, the output amplitude of both circuits decreases due to the gate capacitance and source resistance acting as a low-pass filter. Frequency response plots are generated using a dynamic signal analyzer to observe this effect. The experiment is intended to illustrate how capacitance affects a circuit

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