About this scholarly article

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) - A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic by Kato, Kazunari; Takahashi, Yasuhiro; Sekine, Toshikazu is a scholarly article available to read on EtoBox.

Author

Kato, Kazunari; Takahashi, Yasuhiro; Sekine, Toshikazu

Publisher

IEEE

Published

2015

Language

EN