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This document discusses using pseudo-random generators to prove lower bounds on computational complexity. It defines pseudo-random generators for boolean and arithmetic circuits, and argues that efficiently computable pseudo-random generators with optimal stretch imply circuit size lower bounds. Specifically, it states that a pseudo-random generator against C(s(n),d(n)) circuits that runs in 2O(m) time yields a lower bound against C(s-1(n),d(s-1(n))) circuits. The document outlines an approach to use pseudo

Author

Sangat Baik

Language

EN