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Critical Issues in Clock-Domain Crossing by Prabakaran Ellaiyappan is a document available to read on EtoBox.

What is Critical Issues in Clock-Domain Crossing about?

Critical clock-domain-crossing bugs can occur when signals pass between asynchronous clock domains in system-on-chip (SOC) designs. Two common issues are improper sequencing of data/enable signals and loss of data coherence between related signals. Careful design practices can avoid these problems, including ensuring adequate setup time between data and enable signals, adding handshake logic to prevent data corruption, and avoiding combinational logic on clock domain crossing paths that could introduce glit

Author

Prabakaran Ellaiyappan

Language

EN