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About this Engineering article
Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors by Jeamsaksiri, W.; Jurczak, M.; Grau, L.; Linten, D.; Augendre, E.; De Potter, M.; Rooyackers, R.; Wambacq, P.; Badenes, G. is a Engineering article available to read on EtoBox.
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- Author
- Jeamsaksiri, W.; Jurczak, M.; Grau, L.; Linten, D.; Augendre, E.; De Potter, M.; Rooyackers, R.; Wambacq, P.; Badenes, G.
- Publisher
- IEEE; Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers (IEEE) (ISSN 0018-9383)
- Published
- 2003
- Language
- EN
- Field
- Engineering (Physical Sciences)