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This document describes an area efficient digital comparator design using pseudo nMOS and pass transistor logic. The design uses a novel parallel prefix tree structure to perform bitwise comparisons of two N-bit operands from most significant bit to least significant bit. If the bits being compared are unequal, comparison of lower bits is terminated to reduce switching activity. The results are stored on left and right buses with at most one high bit on each. A decision module then determines if the first o

Author

amta1

Language

EN