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1 General 7 1.1 Scope 7 1.2 Purpose 7 2 References 7 3 Definitions and Nomenclature 8 3.1 Definitions 8 3.2 Nomenclature 11 4 CMOS Latchup Test Structures 12 4.1 Introduction 12 Unguarded Four-Stripe PNPN 12 5 Unguarded Six-Stripe Inverter 20 5.1 Introduction 20 5.2 Output Overvoltage 23 5.3 Output Undervoltage 25 Substrate Current Triggered Latchup 25 6 Test Philosophy 30 6.1 Test Procedure 30 6.2 Hazards 31 IV Characteristic of a Four-Layer SCR Device 9 a PNPN Structure 9 Bipolar LVce Latching Voltage is not SCR Latchup 10 MOS Snapback Voltage is not SCR Latchup 11 Cross-Section of P-Well Unguarded Four-Stripe PNPN Test Structure 13 Topological Layout of Unguarded Four-Stripe PNPN Test Structure 13 Schematic of Four-Stripe PNPN Test Structure 14 Terminal Connections for N-Well Case Two-Terminal Four-Stripe PNPN 15 Terminal Connections for P-Well Case Two-Terminal Four-Stripe PNPN 15 IV Characteristics for Two-Terminal Four-Stripe PNPN 16 Terminal Connections for Output Overvoltage Triggering 17 IV Curves for Output Overvoltage Triggering 17 Terminal Connections for Output Undervoltage Triggering 18 IV Curves for Output Undervoltage Triggering 18 Terminal Connections for the N-Wel

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