About this scholarly article

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems by Huang, Xiaohua; Liu, Han; Rhee, Woogeun; Wang, Zhihua is a scholarly article available to read on EtoBox.

Author

Huang, Xiaohua; Liu, Han; Rhee, Woogeun; Wang, Zhihua

Publisher

IEEE

Published

2018

Language

HA