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This paper presents a high-performance RISC-V vector architecture designed for data-intensive workloads, featuring a 512-bit register file, dynamic bit-width support, and a pipelined matrix multiplication accelerator. The architecture integrates an interrupt-driven finite state machine (FSM) for efficient parallel execution of vector and scalar operations, achieving significant reductions in clock cycles and improved performance for AI and machine learning applications. Benchmarking results demonstrate up t

Author

minakuma678

Language

EN