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What is Power-Efficient 1.8V CMOS Op-Amp Design about?
This paper introduces a power-efficient 1.8 V CMOS operational transconductance amplifier designed for charge pumps in phase-locked loops, utilizing a rail-to-rail input and output range. The amplifier achieves a dc gain of 60.49 dB, a phase margin of 59.64°, and a unity gain frequency of 538.3 MHz while consuming 2.13 mW of power. The design incorporates constant-gm techniques to minimize transconductance variations, enhancing performance across the common mode input range.
- Author
- rahmazerdoumi
- Language
- EN