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What is Delta-Sigma ADC Design and Simulation about?

Our project aims to implement a Delta-Sigma analog to digital converter with a bandwidth of 20 kHz. A second-order switched capacitor filter will be used at the front end along with digital filtering at the back end. The oversampling rate was reduced from 512 to 256 to reduce tones in the noise spectrum. The output bit width was increased to 16 bits. Simulations of the front end in Simulink show it can achieve 16 effective bits and a signal to noise ratio of 95.6 dB with an oversampling rate of 256. Transis

Author

vvigya

Language

EN