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Rigel: an Architecture and Scalable Programming Interface for a 1000-Core Accelerator by John H. Kelm; Daniel R. Johnson; Matthew R. Johnson; Neal C. Crago; William Tuohy; Aqeel Mahesri; Steven S. Lumetta; Matthew I. Frank; Sanjay J. Patel is a scholarly article available to read on EtoBox.

What is Rigel: an Architecture and Scalable Programming Interface for a 1000-Core Accelerator about?

This paper considers Rigel, a programmable accelerator architecture for a broad class of data-and task-parallel computation. Rigel comprises 1000+ hierarchically-organized cores that use a fine-grained, dynamically scheduled singleprogram, multiple-data (SPMD) execution model. Rigel's low-level programming interface adopts a single global address space model where parallel work is expressed in a taskcentric, bulk-synchronized manner using minimal hardware support. Compared to existing accelerators, which contain domain-specific hardware, specialized memories, and restrictive programming models, Rigel is more flexible and provides a straightforward target for a broader set of applications. We perform a design analysis of Rigel to quantify the compute density and power efficiency of our initial design. We find that Rigel can achieve a density of over 8 single-precision in 45nm, which is comparable to high-end GPUs scaled to 45nm. We perform experimental analysis on several applications ported to the Rigel low-level programming interface. We examine scalability issues related to work distribution, synchronization, and load-balancing for 1000-core accelerators using software techniques

Author

John H. Kelm; Daniel R. Johnson; Matthew R. Johnson; Neal C. Crago; William Tuohy; Aqeel Mahesri; Steven S. Lumetta; Matthew I. Frank; Sanjay J. Patel

Publisher

ACM

Published

2009

Language

EN