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8-Bit Floating Point Adder Design Report by Biswajit Kumar Singh is a document available to read on EtoBox.

What is 8-Bit Floating Point Adder Design Report about?

This document provides details on the design of an 8-bit floating point adder/subtractor circuit implemented in Verilog and layout. It includes sections on the chip floorplan, area estimates, simulation results, verification steps, and schematics/layout views. The design consists of a synthesized mantissa datapath combined with a hand-layout exponent datapath. Simulation waveforms showing correct operation are provided from both the Verilog model and post-layout simulations.

Author

Biswajit Kumar Singh

Language

EN