About this document
RTL Design and Synthesis with Cadence by fake god is a document available to read on EtoBox.
This document describes a lab experiment on logic synthesis of a digital circuit design using Cadence tools. The objectives are to use RTL code to generate a synthesized netlist and verify its functionality. Students are instructed to set up work directories, run synthesis on sample code using Genus, and compare pre- and post-synthesis simulation results to analyze the effects of the synthesis process.
- Author
- fake god
- Language
- EN