About this document

Scan Design Methodology for VLSI by sandy_711 is a document available to read on EtoBox.

The document discusses the importance of scan design methodology for producing high-quality chips as gate counts increase enormously. Scan design allows automatic test pattern generation (ATPG) tools to generate test patterns that provide high fault coverage by reducing designs to combinational logic and increasing controllability and observability of internal nodes. Scan design works by connecting storage cells into a long shift register called a scan chain. This allows test patterns to be shifted into the

Author

sandy_711

Language

EN