About this document

1-Bit Adder/Subtractor Design Lab by Alvish Naidu is a document available to read on EtoBox.

The document summarizes an experiment to design and implement a 1-bit adder/subtractor circuit. It includes the objectives, theory behind half and full adders, materials used, methodology, truth table, logic equations, minimized circuit design with 6 logic gates and 3 IC chips, discussion of XOR gates minimizing the sum portion, and conclusions about learning how adders are implemented.

Author

Alvish Naidu

Language

EN