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RPCAcc: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator by Zhang, Jie; Huang, Hongjing; Xu, Xuzheng; Li, Xiang; Zhao, Jieru; Liu, Ming; Wang, Zeke is a scholarly article available to read on EtoBox.

What is RPCAcc: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator about?

The emerging microservice/serverless-based cloud programming paradigm and the rising networking speeds leave the RPC stack as the predominant data center tax. Domain-specific hardware acceleration holds the potential to disentangle the overhead and save host CPU cycles. However, state-of-the-art RPC accelerators integrate RPC logic into the CPU or use specialized low-latency interconnects, hardly adopted in commodity servers. To this end, we design and implement RPCAcc, a software-hardware co-designed RPC on-NIC accelerator that enables reconfigurable RPC kernel offloading. RPCAcc connects to the server through the most widely used PCIe interconnect. To grapple with the ramifications of PCIe-induced challenges, RPCAcc introduces three techniques:(a) a target-aware deserializer that effectively batches cross-PCIe writes on the accelerator's on-chip memory using compacted hardware data structures; (b) a memory-affinity CPU-accelerator collaborative serializer, which trades additional host memory copies for slow cross-PCIe transfers; (c) an automatic field update technique that transparently codifies the schema based on dynamic reconfigure RPC kernels to minimize superfluous PCIe trav

Author

Zhang, Jie; Huang, Hongjing; Xu, Xuzheng; Li, Xiang; Zhao, Jieru; Liu, Ming; Wang, Zeke

Published

2024

Language

EN