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About this Engineering article
Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure by Nakamura, A.; Moriya, H.; Terano, T.; Kosaka, H.; Hashiguchi, A.; Nomoto, K.; Fujiwara, I.; Kobayashi, T.; Oda, T. is a Engineering article available to read on EtoBox.
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- Author
- Nakamura, A.; Moriya, H.; Terano, T.; Kosaka, H.; Hashiguchi, A.; Nomoto, K.; Fujiwara, I.; Kobayashi, T.; Oda, T.
- Publisher
- IEEE; Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers (IEEE) (ISSN 0018-9383)
- Published
- 2004
- Language
- EN
- Field
- Engineering (Physical Sciences)