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3D CMP Design with Network-in-Memory by Cecilia Chinna is a document available to read on EtoBox.

This paper proposes a 3D network-in-memory architecture for chip multiprocessors (CMPs) using a dynamic time division multiple access (dTDMA) bus. The architecture stacks cache banks in 3D to reduce hit latency and improve performance. Caches are divided into clusters, each with its own tag array. Processors are placed on dedicated pillars for fast access to cache banks across layers. Intra-layer communication uses routers while inter-layer uses the more efficient dTDMA bus. Thermal issues from 3D stacking

Author

Cecilia Chinna

Language

EN