About this document
INTC - ISR - CLEAR1 Is Shown in and Described in - This Register Is Used To Clear The Software Interrupt Bits by bscaxsb1117 is a document available to read on EtoBox.
The document details various interrupt controller registers, including INTC_ISR_CLEAR1, INTC_PENDING_IRQ1, INTC_PENDING_FIQ1, INTC_ITR2, and INTC_MIR2. Each register is described with its offset, reset value, and purpose, such as clearing software interrupt bits or showing raw interrupt input status. The document provides figures and tables for visual reference and detailed field descriptions for each register.
- Author
- bscaxsb1117
- Language
- EN