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This document describes the design of a high-speed serializer for interchip data communication. It uses a delay locked loop (DLL) based clock multiplier unit to generate a high-frequency clock from a low-frequency input clock. This clock is then used by a serializer to convert parallel data streams into a single serialized data stream at 2Gbps. The serializer utilizes a tree structure of 2:1 serializers to realize an 8:1 serializer. A pre-charge type phase frequency detector is used in the DLL for better ph

Author

Abderrahim Zahri

Language

EN