About this scholarly article

2011 IEEE Workshop on Signal Processing Systems (SiPS) - A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering by Xie, Qian; He, Qian; Peng, Xiao; Cui, Ying; Chen, Zhixiang; Zhou, Dajiang; Goto, Satoshi is a scholarly article available to read on EtoBox.

Author

Xie, Qian; He, Qian; Peng, Xiao; Cui, Ying; Chen, Zhixiang; Zhou, Dajiang; Goto, Satoshi

Publisher

IEEE

Published

2011

Language

EN