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A Pointcut-based Assertion for High-level Hardware Design by Yusuke Endoh; Takeo Imai; Mikito Iwamasa; Yoshio Kataoka is a scholarly article available to read on EtoBox.

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Verifying very-large-scale integration (VLSI) circuit design using assertions is becoming more common. Herein, an assertion represents a temporal relationship among circuit events over time using temporal logic expression. On the other hand, "high-level design" has also become more common recently. Instead of conventional hardware description languages (HDLs), VLSI designers introduce C-based design languages. Although both of these trends are fairly effective in VLSI development, there is a big gap between these two approaches. Since conventional assertion languages are for conventional HDLs, they only allow specification of change of variables or low-level events raised along with signals. In high-level design, however, there are various high-level events, such as a method call or a state transition which no conventional assertion language can handle. This paper proposes a new assertion language extension, namely, a pointcut-based assertion that enhances an existing assertion language to make assertions available even in high-level design. We introduce a pointcut notion to specify various events from low-level signal-related ones to high-level state transition-related ones. To co

Author

Yusuke Endoh; Takeo Imai; Mikito Iwamasa; Yoshio Kataoka

Publisher

ACM

Published

2008

Language

EN