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A Design of High Speed Double Precision Floating Point Adder Using Macro Modules by Chi Huang; Xinyu Wu; Jinmei Lai; Chengshou Sun; Gang Li is a scholarly article available to read on EtoBox.

What is A Design of High Speed Double Precision Floating Point Adder Using Macro Modules about?

Based on SMIC 0.18 μm 1.8V six-layer-metal CMOS process, we implement a 64-bit high speed pipelined floating point adder which satisfied IEEE 754 standard. After the critical path analysis of the pipelined structure, we custom design three macro modules in order to reduce critical path delay. After placement in datapath style and routing, we implement the layout of floating point adder. The chip area is 1.44 2 mm and clock frequency is 518MHz.

Author

Chi Huang; Xinyu Wu; Jinmei Lai; Chengshou Sun; Gang Li

Publisher

ACM Press

Published

2005

Language

EN